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Popular repositories

  1. FM-partioner FM-partioner Public

    Fiduccia-Mattheyses method to bi-partition the ISPD 2016 benchmarks and minimized the cutset

    C++ 5 4

  2. Design-verification Design-verification Public

    UVM and Systemverilog based test benches for functional verification of a RAM module

    SystemVerilog 5 5

  3. Standard-cell-placement-engine Standard-cell-placement-engine Public

    Simulated Annealing based fixed-die standard cell placement engine for IBM benchmark netlists

    C++ 4 5

  4. MSDAP MSDAP Public

    Complete design of a Mini Stereo Digital Audio Processor

    Verilog 3 4

  5. Physical-Layout-Design Physical-Layout-Design Public

    Complete design of USART interface with baud rate selection

    Verilog 2 2