An FPGA&CPLD engineer in a certain circuit design department.
What a pretty circuit!
Twitter: @AUDIY14
GitHub: AUDIY
- FIR_x2
FPGA based PCM oversampling FIR filter (oversample ratio: 2). - AUDIY_Verilog_IP
Verilog IP that AUDIY originally designed. - AUDIY_OSPCB
Open Source PCB Files Engineered by AUDIY. - DSFIO
DSD Stream File (*.dsf) reader library written in C.
電子回路わからん日記 (https://audio-diy.hatenablog.com/)
- FPGA
- Verilog HDL
- Python
- C/C++
- Audio Signal Processing
- Electronic Circuit Design
- C++
- SystemVerilog (including SVA)
- VHDL
- PSL assertion