Electrical and Computer Engineering ECE 3622 Embedded System Design Dennis Silage, PhD silage@temple.edu
This Spring Junior or Senior elective ECE course with corequisite Laboratory considers Verilog hardware description language (HDL), C/C++ language programming and high level synthesis (HLS) in system-on-chip (SoC) design with the ARM Cortex-A9 processors and the AMBA bus interconnection of the Xilinx Zynq device. The operating system utilized is initially single tasking followed by the multi-tasking, real-time operating system FreeRTOS. The prerequisites are CIS1057 Computer Programming in C, ECE2612/2613 Digital Logic Design and Laboratory and ECE3612/3613 Microprocessor Systems and Laboratory. ECE3622 and ECE3623 co-requisite laboratory is a required course in the Computer Engineering concentration but is available as an elective in the Electrical Engineering and Bioelectrical concentrations in ECE.
The course texts are the The Zynq Book, The Zynq Book Tutorial, the FreeRTOS Real-time Kernel reference and tutorials on Canvas. Coordinated HDL, C/C++ and HLS SoC and RTOS projects using Xilinx Vivado (www.xilinx.com), FreeRTOS (www.freertos.org), the Digilent Zynq Z-7010 Zybo board (digilentinc.com) and Digilent Pmod sensors in ECE3623 Embedded System Design Laboratory are an integral part of the course material.
The grade for ECE3622 consists of four 20 minute SNAP Quizzes (20%), three 60 minute Exams (45%) and comprehensive 120 minute Final Exam (35%). The SNAP Quizzes, Exams, Final Exam and the open ECE3623 laboratory require a laptop computer in-class with the Xilinx Vivado and FreeRTOS design environments.
Week 1. Zynq Book Chapter 1. Embedded SoC, SoC design flow, Zynq SoC Vivado IDE and SDK installation and design flow, Zybo board Zynq Book Tutorials: Exercise 1A IP integrator design, Exercise 1B Zynq system in Vivado
Week 2. Zynq Book Chapter 2. Zynq processing system (PS), programmable logic (PL), AXI interconnect and interfaces, EMIO interfaces Zynq Book Chapter 3. Zynq hardware configuration, Vivado design flow, Zynq Book Tutorials: Exercise 1C Software application in the SDK SNAP Quiz
Week 3. Zynq Book Chapter 4. Device comparisons, soft-core processors Zynq Book Chapter 10. Interrupt interfaces and interconnects Zynq Book Tutorials: Exercise 2A Expanding the basic IP integrator design, Exercise 2B Zynq system with interrupts in Vivado Zynq SPI Peripherals
Week 4. Zynq Book Chapter 10. Generic interrupt controller, interrupt priority Zynq Book Tutorials: Exercise 2C Software application in the SDK, Exercise 2D Further interrupt source First Exam
Week 5. Zynq Book Chapter 14. High level synthesis (HLS). Chapter 15. Vivado HLS Zynq Book Tutorials: 3A Creating projects in Vivado HLS, 3B Design optimization in Vivado HLS Zynq SPI Peripherals, Introduction to DSP
Week 6. Zynq Book Chapter 18. IP reuse and integration Zynq Book Tutorials: 4A Creating IP in HDL, 4C Creating IP in Vivado HLS SNAP Quiz
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Week 7. FreeRTOS Kernel Tutorial Chapter 1. FreeRTOS distribution and data types
Week 8. FreeRTOS Kernel Tutorial Chapter 3. Task management Second Exam
Week 9. FreeRTOS Kernel Tutorial Chapter 4. Queue management
Week 10. FreeRTOS Kernel Tutorial Chapter 5. Software timer management SNAP Quiz
Week 11. FreeRTOS Kernel Tutorial Chapter 6. Interrupt management
Week 12. FreeRTOS Kernel Tutorial Chapter 7. Resource management Third Exam
Week 13. FreeRTOS Kernel Tutorial Chapter 8. Event groups
Week 14. Course review SNAP Quiz
Week 15. Final Exam
Instructor: Dennis Silage, PhD Professor Office: 706E Office Hours: Tuesday 11:00 AM-12:00 PM 1:00-2:00 PM Thursday 1:00-2:00 PM or by appointment Voicemail: 215-204-6761 Email: silage@temple.edu
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Appointments: The preferred, professional manner to schedule an appointment to discuss the material of this course and for questions or concerns is via email.
Accommodation: Any student who has a need for accommodation based on the impact of a disability should contact the Instructor privately to discuss the specific situation as soon as possible. Contact Disability Resources and Services at 215-204-1280 in 100 Ritter Annex to coordinate reasonable accommodations for students with documented disabilities.
Participation and Preparation: Attendance at the lectures is considered as participation and is mandatory.
Course Objectives and Outcomes: The objectives and outcomes for this course (and all courses in ECE) are maintained as part of the ABET accreditation criteria.
Acknowledgement. The ECE3623 laboratory is made possible in part by support from the Xilinx University Program. The TU ECE System Chip Design Laboratory (www.temple.edu/scdl (Links to an external site.)Links to an external site.) conducts graduate research in this area.