Repository of Vivado projects.
Semester - 3
Year - 2021
- System Verilog (for the design source)
- Verilog (for the Test benches)
- Name: Basys 3 Artix-7 FPGA Board
- Family: Artix-7
- Package: cpg-236
- Speed grade: -1
- Part Name:
xc7a35tcpg236-1
- Basic Logic gates and Universal gates.
- MUX and DEMUX (4:1 and 1:4).
- Encoder, Priority Encoder and Decoder.
- Full Adder and Converter.
- D Latch and JK Flip Flop.
- Asynchronous and Synchronous Counters.
- Accumulator.
- Multiplier.
- Moore (One-Hot sequence detector and sequence detector) and Mealy sequence detector.
- Design of memory block (32x4 RAM).
The names have been listed in the order with which they have been written in the lab record.
If the project name is project_name:
- Design source:
project_name/project_name.srcs/sources_1/new - Test Benches:
project_name/project_name.srcs/sim_1/new - Constraint file:
project_name/project_name.srcs/constrs_1/new
The necessary printouts are present in the printouts folder.
Download XILINX Vivado here