Skip to content
View zli87's full-sized avatar
Block or Report

Block or report zli87

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
zli87/README.md
  • 👋 Hi, I’m @zli87
  • 👀 I’m interested in ASIC Design Verification of computer arhictecture
  • 🌱 I plan to learn UVM verification, ASIC accelerator, high level synthesis
  • 💞️ I’m looking to collaborate on RTL design/verification
  • 📫 How to reach me: zli87@alumni.ncsu.edu

Pinned

  1. Processor-and-Accelerator Processor-and-Accelerator Public

    MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement

    Verilog 5

  2. Architecture-of-Parallel-Computers Architecture-of-Parallel-Computers Public

    Simulator for Coherence protocol, parallel programming acceleration with OpenMP, MPI, Hybrid

    C 2

  3. Wishbone-to-I2C-bus-controller-IP-Verification Wishbone-to-I2C-bus-controller-IP-Verification Public

    ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.

    VHDL 12 4

  4. High_Level_Synthesis_for_FPGAs High_Level_Synthesis_for_FPGAs Public

    This resource comes from UCSD’s 237C Parallel Programming for FPGAs. Currently, try to finish this tutorial through vitis_hls 2020.

    VHDL 1

  5. Microprocessor-Architecture Microprocessor-Architecture Public

    Cache_Simulator, Branch_Prediction and Dynamic_Instruction_Scheduling

    C++ 1

  6. Operating-Systems-Principles Operating-Systems-Principles Public

    Implement process scheduling, lock with priority inheritance, demand paging in XINU OS. All projects pass all tests

    C