simulation of a multi-core (with an arbitrary number of cores) cache, including set associativity, with simple MSI cache coherency.
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Updated
Jun 17, 2018 - C
simulation of a multi-core (with an arbitrary number of cores) cache, including set associativity, with simple MSI cache coherency.
Heo is a cycle-accurate multicore architectural simulator written in Go.
Learning ECS - 100k Cubes in Phyllotaxis pattern
A Multi-core MIPS ISA, with MRM and DRAM, Simulator. Prints what is happening in every clock cycle and the final content of registers and DRAM.
Adds multicore processing support to a 64-bit x86 research operating system (InfOS). This involved designing the boot protocol to handle multiple cores, adapting the interrupt system to handle interprocessor interrupts, reworking the scheduler to distribute threads among multiple cores and writing locking primitives that prevent race conditions.
Dedekind numbers and today fastest computers.
Simulator for Coherence protocol, parallel programming acceleration with OpenMP, MPI, Hybrid
A cache coherence simulator for MESI, MOESI and Dragon Protocols.
ConvLIB is a library of convolution kernels for multicore processors with ARM (NEON) or RISC-V architecture
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