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jaycordaro/README.md
  • 👋 Hi, I’m @jaycordaro
  • 👀 I’m interested in ... timing, jitter, FPGAs, electronics, and machine learning

Pinned

  1. spi_slave_simple spi_slave_simple Public

    Simple System Verilog implementation of SPI Slave

    SystemVerilog 3 1

  2. half-band-filter half-band-filter Public

    An implementation of an FIR half-band filter, from MATLAB floating point to SystemVerilog fixed point

    SystemVerilog

  3. i2s-toneplayer i2s-toneplayer Public

    SystemVerilog I2S target, interfaces with an I2S controller. Controller sources WS and SCK

    SystemVerilog

  4. Jays_KiCAD_Library Jays_KiCAD_Library Public

    Symbols and Footprints for some components in KiCAD 5.x

  5. pdmbrd pdmbrd Public

    Analog audio to Pulse Density Modulation (PDM) using OnSemi FAN3852 ICs

    1

  6. WES207 WES207 Public

    Repo for our final project

    Verilog