MIPS32CPU-5stage-pipelined

A 5-stage pipelined mips32 processor

·Finished as a final project for the course "Computer Architecture" in Beihang University.

·FGPA configuration

Family: Spartan6

Device: XC6SLX100

Package: FGG676

Speed: -2

·Instructions supported:

LB、LBU、LH、LHU、LW、SB、SH、SW、ADD、ADDU、SUB、SUBU、SLL、SRL、SRA、SLLV、SRLV、SRAV、 AND、OR、XOR、NOR、ADDI、ADDIU、ANDI、ORI、XORI、LUI、SLT、SLTI、 SLTIU、SLTU、BEQ、BNE、BLEZ、BGTZ、BLTZ、BGEZ、J、JAL、JALR、JR、ERET、MFC0、MTC0

·Interruption supported (Timer and MiniUART can send interruption requests)

·Serial Communication through MiniUART module (RS-232 prototype)

·Forwarding as long as it's possible. Stalling when needed.

Name		Name	Last commit message	Last commit date
Latest commit History 20 Commits
src		src
Arithmetic_Logic_Unit.v		Arithmetic_Logic_Unit.v
Bridge.v		Bridge.v
Byte_Entry_Unit.v		Byte_Entry_Unit.v
Byte_Halfword_Extender.v		Byte_Halfword_Extender.v
CoProcessor0.v		CoProcessor0.v
Comparer.v		Comparer.v
Control_Unit_D.v		Control_Unit_D.v
Control_Unit_E.v		Control_Unit_E.v
Control_Unit_M.v		Control_Unit_M.v
Control_Unit_W.v		Control_Unit_W.v
D_E_Reg.v		D_E_Reg.v
Data_Memory.v		Data_Memory.v
E_M_Reg.v		E_M_Reg.v
Extender.v		Extender.v
F_D_Reg.v		F_D_Reg.v
Forward_Detection_Unit.v		Forward_Detection_Unit.v
Instruction_Decoder.v		Instruction_Decoder.v
Instruction_Memory.v		Instruction_Memory.v
MUX_32bit_2to1.v		MUX_32bit_2to1.v
MUX_32bit_4to1.v		MUX_32bit_4to1.v
MUX_32bit_8to1.v		MUX_32bit_8to1.v
MUX_5bit_4to1.v		MUX_5bit_4to1.v
M_W_Reg.v		M_W_Reg.v
Next_Program_Counter.v		Next_Program_Counter.v
P8.zip		P8.zip
P8_PIN_Verified.ucf		P8_PIN_Verified.ucf
Program_Counter.v		Program_Counter.v
README.md		README.md
Register_File.v		Register_File.v
Stall_Detection_Unit.v		Stall_Detection_Unit.v
cpu.v		cpu.v
driver_LED.v		driver_LED.v
driver_dipswitch.v		driver_dipswitch.v
driver_lights.v		driver_lights.v
driver_userkey.v		driver_userkey.v
mips.v		mips.v
mips_tb.v		mips_tb.v
timer.v		timer.v

jasonlovescoding/MIPS32CPU-5stage-pipelined

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MIPS32CPU-5stage-pipelined

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