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Fast transpile with MixIn #1455

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nkanazawa1989
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Summary

Call to Qiskit transpiler is overkill for simple experiment that directly creates ISA circuits, like T1 and T2 experiment. This PR adds a mixin class that automatically implements _transpiled_circuits() method that only maps virtual qubit index to physical qubit index without invoking the computationally heavy transpiler.

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@wshanks wshanks mentioned this pull request May 16, 2024
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class SimpleCircuitExtenderMixin:
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I wonder if we want to make this a feature of BaseExperiment rather than a mixin. I am not sure what the variable should be called but experiments could set something like layout_and_translate_only = True and if BaseExperiment._transpiled_circuits could just do the code here in that case.

):
# In Qiskit provider model barrier is not included in target.
# Use standard circuit transpile when circuit is not ISA.
return transpile(
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Don't you at least want to set optimization_level? Better than that, could we create a pass manager with just BasisTranslator here?

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Could we quickly check for custom pulse gates as well? I think that is the one other pass that users sometimes want for QE (though in the future that will probably go away).

Comment on lines +91 to +98
p_qregs = QuantumRegister(n_qubits)
v_p_map = {q: p_qregs[self.physical_qubits[i]] for i, q in enumerate(v_circ.qubits)}
p_circ = QuantumCircuit(p_qregs, *v_circ.cregs)
p_circ.metadata = v_circ.metadata
for inst, v_qubits, clbits in v_circ.data:
p_qubits = list(map(v_p_map.get, v_qubits))
p_circ._append(inst, p_qubits, clbits)
return p_circ
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Would the equivalent of this make sense in Qiskit as a SimpleLayout pass? I have not understood why the simplest layout in Qiskit has to be four stages and involve ancilla expansion like it does.

@nkanazawa1989
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close this in favor of #1459

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2 participants