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Pull requests: OpenXiangShan/XiangShan

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Pull requests list

DCache: Move L2 refill error signal to refill_info
#3063 opened Jun 12, 2024 by bosscharlie Loading…
Fix timing of memblock
#3062 opened Jun 12, 2024 by good-circle Draft
Add format checking for XiangShan
#3061 opened Jun 12, 2024 by Yan-Muzi Loading…
Timing optimization for MemScheduler
#3054 opened Jun 11, 2024 by sinsanction Loading…
Frontend new ICache
#3051 opened Jun 7, 2024 by ssszwic Loading…
Update CODEOWNERS about ICache
#3050 opened Jun 7, 2024 by ssszwic Loading…
L1CacheErrorInfo: code refactor for correct and convenient clockgate refactor Just make code pretty security Some designs may introduce security issues
#3044 opened Jun 5, 2024 by Maxpicca-Li Loading…
bpu: use (27, 12, 12) segmented PC in BPU
#3027 opened Jun 1, 2024 by eastonman Loading…
memblock: add rest clockgate of reg. power about power design or optimization
#3017 opened May 28, 2024 by Maxpicca-Li Loading…
Bump huancun: fix dual-core bug
#3013 opened May 27, 2024 by sumailyyc Loading…
ICache: fence.i should flush mainPipe
#3004 opened May 23, 2024 by ngc7331 Loading…
IFU: cut the number of PC registers
#2979 opened May 13, 2024 by my-mayfly Loading…
wpu:fix the issue of abnormal power power about power design or optimization
#2976 opened May 13, 2024 by Maxpicca-Li Loading…
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