HC32: Update Clock Configuration

[shadow578]

Description

Undoes some changes made in in #27086 and updates some comments to reflect the clock architecture on HC32.
Also see #27086 (comment).

With feedback in comments, this PR now also includes a more general overhaul of the HC32 HAL's clock configuration.

HC32 Clock Architecture

This part is meant to provide a high-level overview of the clock architecture used in the HC32 HAL, and how it is configured in Marlin.

In the HC32 HAL, all clocks are derived from the MPLL-P clock, divided by a fixed divider.

First, the MPLL input clock is set to one of three sources:

1. External XTAL @ 8 MHz (if BOARD_XTAL_FREQUENCY == 8 MHz)
2. External XTAL @ 16 MHz (if BOARD_XTAL_FREQUENCY == 16 MHz)
3. Internal high-speed RC oscillator (HRC) @ 16 MHz (if neither 1 nor 2)

The MPLL then locks onto the input clock divided by an internal division factor M.
The resulting clock is then multiplied by internal factor N, before beign divided by factors P, Q and R to create the equally named output clocks (MPLL-P, MPLL-Q and MPLL-R).
MPLL-Q and MPLL-R are not used by the HC32 HAL, so can be ignored.
These values are configured in the pllConf struct.

(Final MPLL-P output clock is calculated as $ f_{P} = \frac{\frac{f_{in}}{M} * N}{P} $.)

The MPLL-P clock is then divided by the dividers configured in the sysClkConf struct to get the final output clocks.
For example, HCLK = MPLL-P / 1 and PCLK2 = MPLL-P / 8.

To ensure all clocks are valid, they are verified using the assert_system_clocks_valid function (when available).

See Fig. A for a marked up clock system block diagram highlighting the path of the various clocks used in the HC32 HAL.
Also consider referencing Section 4.2.1 of the HC32F460 Reference Manual if more information is needed.

Requirements

HC32-based printer

Benefits

Updates documentation for HC32 HAL clock configuration.

Configurations

N/A

Related Issues

N/A

Attachments

Fig. A: Clock System Block Diagram

[thinkyhead]

I see… Since F_CPU is not the "master value" but there is a common clock value on which the others are based, we should define that at least, and then define the others in terms of that. We would call it F_HCLK (or something even more specific)…

#define F_HCLK 200000000 // 200MHz HCLK
#define F_CPU F_HCLK

[thinkyhead]

I pushed a commit with what makes sense to me, but of course please apply corrections and clarifications. It's interesting that HC32 clock frequency is so configurable, and it will be cool to be able to change the clock speed by changing a single define.

[shadow578]

We would call it F_HCLK (or something even more specific)…

it will be cool to be able to change the clock speed by changing a single define.

I think i've got an idea how most of the clock configuration can be handled automagically at compile time, with validation and everything.
Making it a single define is probably not viable tho...
So i'd set it up so each of the clocks can be set to a target frequency individually, and the dividers are then calculated and checked automatically.

PLL config seems a bit daunting to make automatic, so i'll put that off for now :D

I'll push a commit tomorrow, gotta test this first.

---

It's interesting that HC32 clock frequency is so configurable

Yeah, it's kinda weird how capable and configurable this MCU actually is.
When i first started, i thought of it as a STM32 clone.
But as i get more familiar with this chip, i really don't think it's just a clone...
Like, STM32 doesn't have freely configurable interrupt vectors, and also not multiple DMA and ADC units, basically fullly muxed GPIO, and USB (at least i think so).

But then there's also some really weird additions, like two independent watchdog timers...

Anyway, it's a really interesting if not weird chip

[thinkyhead]

Thanks for the feedback, looking forward to your update!

[shadow578]

So, i've pushed a commit to automatically handle everything related to the clock configuration using defines in sysclock.h.
Right now, everything is derived from F_HCLK, but this system is fairly flexible so a different 'main' clock could also be chosen.

PLL config was indeed fairly daunting, but i did manage to pull it off - at least kind of.
When including the M input division factor in the PLL calculations, the call constexpr stc_clk_mpll_cfg_t pllConf = get_mpll_config(mpll_input_clock, F_SYSTEM_CLOCK); shows as an error in vscode.
Compiling does seem to work tho...

Maybe someone whos a bit more skilled in C++ could take a look ?