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rising edge of the clock
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rising edge of the clock
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wlister/README.md

Hi there!

animated 

module top_module (
    input clk,
    input reset,
    output [9:0] q);
	
    always_ff@(posedge clk) begin
        if(reset || q == 999) begin
            q <= 10'd0;
        end
        else begin
            q <= q + 10'd1;
        end
    end
endmodule

Languages and tools I am familiar with

SystemVerilog Java C C++ SQL Python
FPGA ModelSim Quartus IntelliJ Visual Studio Code VSCodium STM32 MySQL Linux Ubuntu Fedora

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