Skip to content
This repository has been archived by the owner on Jun 2, 2024. It is now read-only.

TinyTapeout/tt07-verilog-template

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

10 Commits
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

Tiny Tapeout Verilog Project Template

What is Tiny Tapeout?

Tiny Tapeout is an educational project that aims to make it easier and cheaper than ever to get your digital and analog designs manufactured on a real chip.

To learn more and get started, visit https://tinytapeout.com.

Set up your Verilog project

  1. Add your Verilog files to the src folder.
  2. Edit the info.yaml and update information about your project, paying special attention to the source_files and top_module properties. If you are upgrading an existing Tiny Tapeout project, check out our online info.yaml migration tool.
  3. Edit docs/info.md and add a description of your project.
  4. Adapt the testbench to your design. See test/README.md for more information.

The GitHub action will automatically build the ASIC files using OpenLane.

Enable GitHub actions to build the results page

Resources

What next?

About

Submission template for Tiny Tapeout 7 - Verilog HDL Projects

Resources

License

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published