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Add APX ISA extension #450

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Add APX ISA extension #450

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flobernd
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@flobernd flobernd commented Sep 12, 2023

### Open Tasks
- [x] Rename ISA-set of some existing definitions to be able to distinguish between the new ones
- [x] Add APX mode
- [x] Support new registers in `ZydisRegisterGetLargestEnclosing`, etc.
- [ ] Report DFV flags in public struct

@flobernd flobernd changed the title Add AMX ISA extension Add APX ISA extension Sep 12, 2023
@@ -88,6 +88,12 @@ ZyanStatus ZydisGetInstructionSegments(const ZydisDecodedInstruction* instructio
segment_size = 4;
break;
default:
if (instruction->attributes & ZYDIS_ATTRIB_HAS_REX2)
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This should check encoding instead.

@@ -777,6 +810,10 @@ static void PrintAVXInfo(const ZydisDecodedInstruction* instruction)
ZydisRegisterGetString(instruction->avx.mask.reg),
CVT100_OUT(COLOR_VALUE_LABEL), CVT100_OUT(COLOR_VALUE_B),
strings_mask_mode[instruction->avx.mask.mode], CVT100_OUT(COLOR_VALUE_LABEL));
if (instruction->attributes & ZYDIS_ATTRIB_HAS_SCC)
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We should probably put this in a dedicated APX section together with the "zu" (which is not implemented yet at all).

@@ -2351,6 +2402,8 @@ static void ZydisSetAVXInformation(ZydisDecoderContext* context,
const ZydisInstructionDefinitionEVEX* def =
(const ZydisInstructionDefinitionEVEX*)definition;

// TODO: Don't set vector length, etc. for scalar instructions
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This requires a dedicated flag and generator support.

break;
}

ZyanBool illegal_rex2 = (instruction->opcode == 0x0F);
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Might be better to just generate a flag for this in the generator based on the same condition. We usually try to not hardcode table related conditions.

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There are as well XSAVE and XRSTORE variants that do not support REX2.

(instruction->opcode_map == ZYDIS_OPCODE_MAP_MAP4) &&
(instruction->raw.evex.pp == 0x01))
{
// EVEX encoded instructions in MAP4 must use 0x66 as the mandatory prefix AND the
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Might be better to have a flag for this. We usually don't hardcode table related conditions.

return ZYDIS_STATUS_DECODING_ERROR;
}

// TODO: NF without ND filter -> evex.b = zero upper
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Generator flag would be better here.

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EVEX.b is actually EVEX.ND in these cases.


// All APX conditional CMP and TEST instructions must have a SCC filter!

context->vector_unified.vvvv = (~context->vector_unified.vvvv) & 0x0F;
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This is clumsy.. It would be nice if the generator emits a hint about the EVEX variant to use. We are currently just "guessing".

src/Decoder.c Show resolved Hide resolved
@flobernd flobernd changed the base branch from master to ud0-compat January 22, 2024 14:01
@@ -1009,6 +1053,7 @@ static void ZydisSetOperandSizeAndElementInfo(const ZydisDecoderContext* context
#ifndef ZYDIS_DISABLE_AVX512
if (definition->size[context->eosz_index])
{
// TODO: fixme
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This block is not entered for some tile instructions, resulting in a panic.

Base automatically changed from ud0-compat to master January 26, 2024 19:34
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