MIPS32 ISA Synthesizable CPU (with L1 Cache) RTL Design

Designed a 5-stage all-round scalar processor, synthesized using 45nm library and reached 152MHz;

Pipeline is designed fully bypassed. Finished all the logic/algorithm/jump/branching/load/store instructions as wel as interrupt/systemcall/trap handling mechanisms. Finished co-processor, stall controller and delay slots;

Finished 4KB, 4-way associative Cache with LRU policy and Write-back mode. Also finished a Store Buffer;

Completed an simple SoC using open source Wishbone connecting CPU and I/D Memories.