Virtual processor co-simulation and co-design element for Verilog and VHDL environment.
Allows native C/C++ programs or Python scripts to co-simulate with Verilog, SystemVerilog or VHDL simulations, with a memory mapped read/write interface and support to model interrupts. This enables virtually limitless possibilities for control of a simulation from C/C++ or Python programs, running as if on the instantiated virtual processor in the logic simulation. User code could be as simple as linear test program to drive pattrens on the bus, software models of processors and other SoC components, or embedded software, amongst other things. The software running on the virtual processor can be debugged using such standard tools such as gdb and related IDE applications such as Eclipse.
Currently supported simulators:
- ModelSim : Verilog with PLI or VPI, VHDL with FLI
- Questa : Verilog with PLI or VPI, VHDL with FLI
- Icarus : Verilog with PLI or VPI
- Vivado Xsim : SystemVerilog with DPI-C
- Verilator : SystemVerilog with DPI-C
- NVC : VHDL with VHPIDIRECT
- GHDL : VHDL with VHPIDIRECT
More information can be found in the documentation located in doc/VProc.pdf and related articles on virtual processors, co-simulation and VProc can be found here and here to complement the information in the manual.
The diagram below shows the VProc component that's instantiated in the HDL.
The diagram below shows the stack for node 0 from the HDL environment (Verilog in this diagram) through to the user code—in this case, python. For the C/C++ environment, the stack tops out at VUserMain0() as the user code entry point, with any additional user hiearchy on top of this.
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