Issues: verilog-to-routing/vtr-verilog-to-routing
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Giant distance from initial placing and routing solution to a better one VTR could have found.
#2544
opened Apr 25, 2024 by
WindFrank
3d switch block code, architecture files & reg tests
#2534
opened Apr 11, 2024 by
vaughnbetz
5 tasks
Parmys fails to properly handle multipliers with unequal input widths
#2532
opened Apr 11, 2024 by
WhiteNinjaZ
Remove Warnings in VTR CI Builds
build
Build system
#2518
opened Mar 27, 2024 by
AlexandreSinger
9 of 16 tasks
Add wire length attribute to RR graph output XML when using "--write_rr_graph" option
#2503
opened Mar 14, 2024 by
StephenMoreOSU
Designs with many different wire types fail at certain channel widths with an arithmetic exception
#2497
opened Mar 5, 2024 by
WhiteNinjaZ
Change RRG storage to keep (drive pt, direction) instead of (start, end)
#2491
opened Feb 20, 2024 by
duck2
VPR Placer runtime issue when all design clusters have fixed locations
#2484
opened Feb 5, 2024 by
rachelselinar
Update documentation for .place file to say the block name can be a cluster name or a primitive name within it
#2439
opened Nov 13, 2023 by
vaughnbetz
Regarding the issue of running generate_cmos_tech_data.pl with hspice 2017
#2424
opened Oct 23, 2023 by
luck-codeer
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