COMP.CE.240 Logic Synthesis

Name		Name	Last commit message	Last commit date
Latest commit History 80 Commits
32-master		32-master
B01		B01
B02		B02
B03		B03
B04		B04
B05		B05
E01		E01
E02		E02
E03		E03
E04		E04
E05		E05
E06		E06
E07		E07
E08		E08
E09		E09
E10		E10
E11		E11
E12		E12
E13		E13
my_lib		my_lib
syn/synth_top		syn/synth_top
tb		tb
test		test
verilog		verilog
vhd		vhd
vid		vid
work		work
xdc		xdc
Ex12 command.txt		Ex12 command.txt
README.md		README.md
ard-audio-da7212-user-manual-rev1-0.pdf		ard-audio-da7212-user-manual-rev1-0.pdf
da7212_datasheet_3v4.pdf		da7212_datasheet_3v4.pdf
input.txt		input.txt
modelsim.ini		modelsim.ini
ref_results.txt		ref_results.txt
vsim.wlf		vsim.wlf
wlft210kei		wlft210kei
wlft4f2i97		wlft4f2i97
wlftbbmcj0		wlftbbmcj0
wlftd9a10n		wlftd9a10n
wlfthf6t99		wlfthf6t99
wlfthva654		wlfthva654

trinhgiahuy/LogicSynthesis