Add some documentation on AMD Versal AIE CGRA

[keryell]

No description provided.

[agozillon]

Pretty exciting document update, very happy to see this side of the project is gaining traction again! :-) Unfortunately my team doesn't have access to any of these boards on a server or I'd give it a try!

[keryell]

Pretty exciting document update, very happy to see this side of the project is gaining traction again! :-) Unfortunately my team doesn't have access to any of these boards on a server or I'd give it a try!

Thanks. We are now targeting mostly the AIE CGRA coming along RyzenAI CPU. The plan is to use this project as a CPU simulation back-end for https://github.com/Xilinx/mlir-aie and a modern C++ front-end using MLIR https://github.com/llvm/clangir to target https://github.com/Xilinx/mlir-air and https://github.com/Xilinx/mlir-aie
Perhaps you can add your Fortran front-end too? ;-)