yosys
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Sipeed Tang Nano: Fully Opensource Toolchain for FPGA Synthesis, Place & Route, and Download/Flash.
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May 28, 2024 - Makefile
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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May 28, 2024 - Python
A eurorack-friendly audio frontend compatible with many FPGA boards.
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May 23, 2024 - SystemVerilog
SystemVerilog to Verilog conversion
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May 23, 2024 - Haskell
A modern hardware definition language and toolchain based on Python
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May 18, 2024 - Python
Unofficial nextpnr WebAssembly packages
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May 18, 2024 - Shell
An abstraction library for interfacing EDA tools
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May 17, 2024 - Python
VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
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May 12, 2024 - C
Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)
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May 8, 2024 - Verilog
Pre and Post Synthesis Simulation of a Design VSDMemSOC
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May 5, 2024 - Verilog
Examples for the Lushay Labs tang nano 9k series
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Apr 30, 2024 - GLSL
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