phoeniX RISC-V Processor
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Updated
May 23, 2024 - Verilog
phoeniX RISC-V Processor
Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
Top-level repository for the ACT EDA flow
Deep learning toolkit-enabled VLSI placement
A collection of Schematics, PCBs and VLSI work on various platforms
A browser-based SPICE circuit simulator
Requirements for VLSI front-end Engineer
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Online viewer of Xschem schematic files
GDSII file format parser for JavaScript
In this project, I conducted an in-depth comparative analysis of various adder architectures to assess their performance in terms of delay and power consumption.
ACT hardware description language and core tools.
Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”
Standard Cell Library based Memory Compiler using FF/Latch cells
Micro-Framework for FPGA / VLSI Design Flow in Python
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