OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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Updated
May 23, 2024 - Python
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Deep learning toolkit-enabled VLSI placement
A High-performance Timing Analysis Tool for VLSI Systems
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
phoeniX RISC-V Processor
Open source software for chip reverse engineering.
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor
Standard Cell Library based Memory Compiler using FF/Latch cells
A modern and open-source cross-platform software for chips reverse engineering.
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
ACT hardware description language and core tools.
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
DATC RDF
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
Global Router Built for ICCAD Contest 2019
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
VLSI EDA Global Router
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