Skip to content
#

vivado-ip-integrator

Star

Here are 9 public repositories matching this topic...

Language: All
Filter by language
All 9 VHDL 4 C 3 TeX 1

aryan-programmer / axi_stream_array_sum_microblaze

Star 1

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado microblaze axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls
  • Updated Dec 3, 2023
  • C

Improve this page

Add a description, image, and links to the vivado-ip-integrator topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the vivado-ip-integrator topic, visit your repo's landing page and select "manage topics."

Learn more