Verilator open-source SystemVerilog simulator and lint system
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Updated
Jun 4, 2024 - C++
Verilator open-source SystemVerilog simulator and lint system
HDL support for VS Code
VeeR EL2 Core
System Level Simulation and ASIC hardening flow for various designs using Systemverilog, Verilator and OpenROAD
A small, light weight, RISC CPU soft core
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
FPGA based GPU for rendering ray marched scenes.
An abstraction library for interfacing EDA tools
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
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