Verilator open-source SystemVerilog simulator and lint system
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Updated
Jun 3, 2024 - C++
Verilator open-source SystemVerilog simulator and lint system
RISC-V CPU Core (RV32IM)
VeeR EH1 core
An abstraction library for interfacing EDA tools
A small, light weight, RISC CPU soft core
32-bit Superscalar RISC-V CPU
HDL support for VS Code
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
VeeR EL2 Core
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
A simple, basic, formally verified UART controller
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
A utility for Composing FPGA designs from Peripherals
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
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