rv32im
Here are 22 public repositories matching this topic...
A self-hosting and educational C optimizing compiler
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May 7, 2024 - C
32 Bits RISC-V Processor with Approximate Functions
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Jul 20, 2023 - Verilog
Attempt at building entirely from scratch a RISC-V SoC for self-education purposes.
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Jul 15, 2023 - SystemVerilog
herve, the rv simulator is a simple risc-v RV32IMA ISA simulator.
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Nov 2, 2021 - Assembly
The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWa…
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Oct 31, 2021 - Verilog
RISC-V CPU Core (RV32IM)
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Sep 18, 2021 - Verilog
32-bit Superscalar RISC-V CPU
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Sep 18, 2021 - Verilog
Trivial RISC-V Linux binary bootloader
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Apr 3, 2021 - C
A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
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May 10, 2020 - Verilog
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