OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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Updated
May 25, 2024 - Verilog
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Photonic Integrated ELectronics. Microservices to codesign photonics, electronics, quantum, and more.
SUF is a SUperset Framework for OpenROAD that acts as an enhancement graft by augmenting the original capabilities.
VSDMemSOC Implementation flow:: RTL2GDSII
Physical Design of Mixed signal circuit that performs- "In Memory logic using 8TSRAM cells" using OPENFASOC.
"High density" digital standard cells for SKY130 provided by SkyWater.
9 track standard cells for GF180MCU provided by GlobalFoundries.
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