openroad
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VSDMemSOC Implementation flow:: RTL2GDSII
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Mar 1, 2024 - Verilog
Physical Design of Mixed signal circuit that performs- "In Memory logic using 8TSRAM cells" using OPENFASOC.
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Jul 11, 2023 - Python
SUF is a SUperset Framework for OpenROAD that acts as an enhancement graft by augmenting the original capabilities.
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Apr 7, 2024 - Python
"DSDM2" project @ Politecnico di Milano // AY 2019-2020
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Aug 10, 2020 - Tcl
Running OpenROAD cloud flow on AES design
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Aug 7, 2019 - Verilog
"Low power" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"High voltage" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"High speed" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
Standard cells for SKY90FD provided by SkyWater.
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Jul 28, 2022
"High density, low leakage" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"Medium speed" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
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Feb 22, 2024 - Verilog
"Low speed" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
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