SoC and Embedded Linux
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Updated
Nov 21, 2023 - JavaScript
SoC and Embedded Linux
Matrix multiplication on multiple Nios II cores
A Deep Neural Network-inference accelerator is created in hardware. The codes for hardware is written in System Verilog. The hardware module is interfaced with NIOS computer system, thus this hardware acts as a peripheral to the computer system. The driver code to interface the hardware is written in C. Speedup compard to software is 400 times.
Design MMU for socfpga-linux 4.11. Test with Altera DE2-115.
FPGA SOC Mario NES in SystemVerilog. Built on a DE-10 Lite FPGA, synthesized in Quartus Prime 18.1
Guitar amp sim for Altera DE1-SoC NIOS2
Various VGA video output projects on the NIOS II processor
A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)
Hardware Description Languages
Trivia game programmed in Assembly using NIOS II instruction set - FINISHED BETA TESTING - VERSION 1.00 RELEASED!
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