Ada-language framework

Matrix multiplication on multiple Nios II cores

POSIX-compatible tiny multi-threading library for Intel Nios II / Xilinx Zynq-7000

A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

ECE 385 Final Project -- Ethernet on MAX10 DE10-Lite FPGA and Nios II soft processor

FPGA SOC Mario NES in SystemVerilog. Built on a DE-10 Lite FPGA, synthesized in Quartus Prime 18.1

Various VGA video output projects on the NIOS II processor

Connect a modern, high-resolution camera to an FPGA and easily develop your applications

Design for board DE2-115, microprocessor soft running a uCOS-II(Real Time Operating System). Application to test is a Lift program

Transfers data from an ADC to a PC via ethernet

A Deep Neural Network-inference accelerator is created in hardware. The codes for hardware is written in System Verilog. The hardware module is interfaced with NIOS computer system, thus this hardware acts as a peripheral to the computer system. The driver code to interface the hardware is written in C. Speedup compard to software is 400 times.

Design MMU for socfpga-linux 4.11. Test with Altera DE2-115.

PS/2 keyboard/mouse interfaces for Terasic's DE1-SoC platform — SystemVerilog/C/Nios II

Hardware Description Languages

A compiler for a custom made language to control robots.

Code from FPGA programming with the Altera Nios II

Trivia game programmed in Assembly using NIOS II instruction set - FINISHED BETA TESTING - VERSION 1.00 RELEASED!

Detect musical notes from patterns drawn on the white paper

Code for ELEC 274 Computer Architecture Course

Please check out the attached link.