A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

5-stage pipelined 32-bit MIPS microprocessor in Verilog

It's all coming back into focus!

Some of my assembly code (examples, iterative and recursive algorithms) from Computer's Architecture course in Sapienza University, CS Bachelor's Degree 💾

simulator of a MIPS processor in C

Core part of a mini processor simulator called MySPIM using the C language on a Unix/Linux platform. MySPIM demonstrates some functions of the MIPS processor as well as the principle of separating the data-path from the control signals of the MIPS processor. The MySPIM simulator reads in a file containing MIPS machine code (in a specified the fo…

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Linux kernel source tree with the latest features and modifications to unleash the full potential of Ingenic processors.

MIPS simulator written in Go

Solution for the assignment in Digital Design and Computer Architecture course including test benches running faster than official nightly tests.

A low power, high performance 32-bit, 5-cycle MIPS core that implements a subset of instructions.

A 5-stage pipelined mips32 processor

Simulation of Designs of Basic Computer & Processor Architecture(4-bit MIPS CPU, Floating Point Adder) in Logisim as assignments of Computer Architecture Sessional course of CSE 306 of CSE, BUET

Heo is a cycle-accurate multicore architectural simulator written in Go.

Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding cont…

Modification of the MARS program originally written by Kenneth Vollmar and Pete Sanderson at Missouri State University.

A 2-stage Pipelined MIPS Processor in Verilog

Assignments done in CSE306 course offered by CSE, BUET

🐢 用 Verilog 实现的单周期 MIPS 指令集的 CPU，并用它来计算斐波那契数。