Arquitectura de Computadoras 2018-2019
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Updated
Dec 21, 2020 - VHDL
Arquitectura de Computadoras 2018-2019
Me playing with FPGAs & the Linux kernel
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
This will be my starting point for learning microblaze softcore processor
A Xilinx Vivado project to implement a Microblaze SOC on FPGA to run C applications
C library for shared memory and messaging using inter processor interrupts.
FPGA based Embedded Systems module assignment
International Data Encryption Algorithm implementation for FPGA (in VHDL) and Microblaze processor for FPGA (in C)
A guide illustrating how to use the Digilent GPS PMOD
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
Personal FPGA Proyects mostly Xilinx / Vivado and Some Multisim
Xilinx Microblaze GNU gcc toolchain (including gdb) for Debian Linux with additional fixes and patches
32-bit MIPS processor implementation
Repo documenting steps to run u-boot on Microblaze without PetaLinux wrappers.
codes of my IUT FPGA LAB
CS M152B Codebase Fall 2018
MSc. (DSE UoY) project documentation and partial source code
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