Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.
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Updated
Aug 3, 2022 - Verilog
Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.
Code collective of my 3rd Semester at ITER
implementation of a machine executes simple operations in general built-in registers in Verilog
A Novel Numeric Decoder Logic Design
This repository contains all the stuff that I have learned at MERL-UIT during the training session. This is available for everyone so you can check that out for learning stuff as well.
Course Project for EE224 (Digital Systems) offered in Autumn 2023
Final examination of Digital Logic Design course (Reti Logiche) - A.Y. 2018/2019 Politecnico di Milano
Course website for ECE275: Sequential logic systems, Fall 2021 for the University of Maine
Microprocessor design with Quartus by using Verilog Programming.
This is a test project to implement digital logic design using Logic Works 4
A Digital Logic Design based project working the implementation of Stack Data Structure using all the gates including AND,OR,XOR,XNOR and MUX.Works on LogicWorks 5
Digital Logic Design (.circ) related files can be found here. You must run those files in Logisim software.
This Project is about 7 segment display of an ID using Different Gates and Multiplexers,Decoders
Basic Microprocessor Design in HDLs like Verilog.
Digital logic gate simulator using React, TypeScript and p5.js
VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay
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