Here are
26 public repositories
matching this topic...
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
Updated
Apr 8, 2024
SystemVerilog
Updated
Oct 16, 2017
Verilog
SPD Reader & Writer with Software Write Protection capabilities supporting Arduino and SMBus
Open-sourced DDR3 controller
Updated
May 26, 2024
Verilog
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
Updated
Dec 1, 2022
Verilog
Open hardware compute module with Allwinner A13 (ARM-A8 @1GHZ ), DDR3 (max 512MB) and expansions (USB, GPIO, WiFi, LCD, Audio)
在FPGA中将图像数据输入到DDR3中,再输送到HDMI接口上进行显示。
SpaceVNX (VITA 74.4) carrier based on Zynq-7000.
A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
Updated
May 10, 2020
Verilog
4-Layer XC7Z010 DDR3 Layout
将图像数据从以太网传输到DDR3,再传输到HDMI进行显示的vivado例程
DDR3 controller for nMigen (WIP)
Updated
Dec 25, 2023
Python
A DDR3 to DDR3L (and vice-versa) converter
Updated
Jul 19, 2023
OpenSCAD
Updated
May 8, 2023
OpenSCAD
Test SBC with Allwinner A13
A curated list of awesome Rowhammer papers, tools, and info resources. 👉 Content coming soon, stay tuned!
Improve this page
Add a description, image, and links to the
ddr3
topic page so that developers can more easily learn about it.
Curate this topic
Add this topic to your repo
To associate your repository with the
ddr3
topic, visit your repo's landing page and select "manage topics."
Learn more
You can’t perform that action at this time.