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The Rocks Community profile and public information
show the learning progress on 'chisel' + 'risc-v', build the docs based on vuepress-hope-theme.
Updated
Apr 17, 2024
TypeScript
Multicycle processor in Chisel3
Updated
May 30, 2022
Verilog
Updated
Jan 12, 2022
Scala
OpenSoC Fabric - A Network-On-Chip Generator
Updated
Jan 16, 2024
Scala
Tools to optimize your linux server and config your vpn tunnel
Updated
Apr 19, 2024
Python
Chisel scripts created to debug any issues
Declarative containerized chisel for punching holes through networks
Wierton's OoO processor. Implement ISA MIPS32 Release 1 and 2, can run linux (under development).
Updated
Jun 3, 2022
Scala
RISC-V 1 and 5-stage CPUs Described in Chisel for Implementation in an Altera FPGA
Updated
Oct 15, 2017
Scala
My interests and some collaborations
A 5-stage pipelined RISC microprocessor written in Scala using Chisel
Updated
May 23, 2022
Verilog
Test enviroment to connect jigsaw devices w/ Ibex core in CHISEL & compile the design w/ CIRCT IR to analyze the dumped SV
Updated
Oct 4, 2022
SystemVerilog
Open source flow for generating bitstreams from Chisel code
Updated
Oct 6, 2023
Makefile
Repo for docker hub auto builds
Updated
Oct 19, 2020
Dockerfile
[AFK] Hardware router in Chisel (THU Network Joint Lab 2020)
Updated
Oct 8, 2020
Scala
Updated
Jun 3, 2022
Verilog
Implementation of RISC-V Pipeline
Updated
Mar 2, 2023
Scala
<Digital Design with Chisel> 中译版 <Chisel 数字电路设计>
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