Skip to content
View BoChen-Ye's full-sized avatar
🏠
Working from home
🏠
Working from home
4 followers · 6 following
Block or Report

Block or report BoChen-Ye

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
BoChen-Ye/README.md
  • 👋 Hi, I’m Bochen, a Master student in TU/e, Netherlands.
  • 👀 I’m interested in ASIC/SoC/FPGA Design.
  • 🤔 I'm looking for PhD position or full-time postion at company in related area.
  • 🔭 I’m currently working on a new protocol @ NXP. Before that, I am a intern @ Synopsys for ECC hardware codec.
  • 🌱 I plan to learn SoC, ASIC accelerator for deep learning, Neuromorphic hardware, Multi-core Architecture with NoC.
  • 💞️ I’m looking to collaborate on RTL design/verification.
  • 📫 How to reach me: b.ye@student.tue.nl

Pinned

  1. Tiny_LeViT_Hardware_Accelerator Tiny_LeViT_Hardware_Accelerator Public

    This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.

    SystemVerilog 1

  2. BoChen-Ye.github.io BoChen-Ye.github.io Public

    Forked from RayeRen/acad-homepage.github.io

    AcadHomepage: A Modern and Responsive Academic Personal Homepage

    SCSS 1

  3. OpenSoCFabric OpenSoCFabric Public

    Forked from schoeberl/OpenSoCFabric

    OpenSoC Fabric - A Network-On-Chip Generator

    Scala 2

  4. RISC-V-five-stage-CPU RISC-V-five-stage-CPU Public

    This is a project base on book 'Digital design and computer architure RISC-V edition'. I use Verilog to build RISC-V CPU.

    Verilog 2

  5. Network-on-Chip-Router-Based-on-Packet-Connected-Circuit Network-on-Chip-Router-Based-on-Packet-Connected-Circuit Public archive

    This is my bachelor graduation project. It's a Network on Chip using by Verilog HDL. This 2D-Mesh NoC based on packet connected circuit.

    Verilog

  6. SpkingNN-on-Chip SpkingNN-on-Chip Public

    This is a collection of papers I read on SNN accelerators.

    1