This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
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Updated
May 4, 2024 - SystemVerilog
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle
Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.
A test IP that receives a packet from the NoC, increments its the payload, and sends the packet back to the source
A demonstrator of Hermes network-on-chip communicating with the ARM processor
Zynq PS connected to a Hermes networkn-on-chip router via AXI streaming interface
Synchronous and Asynchronous FIFO with AXI interface
Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)
A collection of formal properties for hardware buses, and cores using them.
Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
Open-Source AXI4 DMA Engine in SystemVerilog and Chisel
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