axi4
Here are 48 public repositories matching this topic...
Synchronous and Asynchronous FIFO with AXI interface
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Nov 20, 2019 - SystemVerilog
A collection of formal properties for hardware buses, and cores using them.
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Feb 22, 2021 - Verilog
RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle
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Apr 7, 2024 - Verilog
A test IP that receives a packet from the NoC, increments its the payload, and sends the packet back to the source
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Jul 25, 2020 - Tcl
Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.
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Aug 3, 2023 - VHDL
Zynq PS connected to a Hermes networkn-on-chip router via AXI streaming interface
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Aug 8, 2020 - Tcl
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
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May 4, 2024 - SystemVerilog
Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
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Sep 21, 2022 - VHDL
Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)
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Oct 13, 2020 - C++
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