VHDL implementation for SiLabs SI5338 Clock Generator with ClockBuilder support.
A Python and MATLAB parser for the header file from ClockBuilder is available as well as a demo project created with Xilinx ISE 14.4.
Please make sure to regenerate the single port rom (generated with Xilinx CoreGen) with read depth 512 and write width 24. Use e.g. the attached coe file (250 MHz clock output) or create with the python or matlab parser a customized one. Make sure that the coe file is correctly given within CoreGen.
ATTENTION: Usually Xilinx ISE uses full path when specifying coe files, but it could be set manually to be relative. Change the file ipcore_dir/mem_si5338.xco, such that it looks as follows:
CSET coe_file=..\si5338_coe.coe
But when editing the CoreGen file with ISE, the path is set to an absolut afterwords, when the COE is not existing a pesudo CoreGen file is used instead and whenever opening the CoreGen file again, the default settings are set instead of the previous chosen one.
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