Merge pull request #44 from siliconcompiler/fix-floorplan

fix floorplan

build.py

@@ -354,6 +354,12 @@ def configure_top_chip(core_chip=None):
     # OpenROAD settings
     chip.set('tool', 'openroad', 'task', 'route', 'var', 'grt_macro_extension', '0')
 
+    for met, adj in (('met2', 0.2),
+                     ('met3', 0.1),
+                     ('met4', 0.1),
+                     ('met5', 0.1)):
+        chip.set('pdk', 'skywater130', 'var', 'openroad', f'{met}_adjustment', '5M1LI', str(adj))
+
     for task in chip._get_tool_tasks(openroad):
         chip.add('tool', 'openroad', 'task', task, 'var', 'psm_skip_nets', 'ioring*')
         chip.add('tool', 'openroad', 'task', task, 'var', 'psm_skip_nets', 'v*io')

floorplan.py

@@ -49,43 +49,47 @@ def generate_core_pins(chip):
     we_pads, no_pads, ea_pads, so_pads = define_io_placement()
 
     # Filter out GPIO pins
-    for i in range(we_pads.count(GPIO)):
+    ea_pins = len(pins) * ea_pads.count(GPIO)
+    for i in range(ea_pads.count(GPIO)):
         order_offset = len(pins) * i
         for pin_order, pin_spec in enumerate(pins):
             pin, bit, width = pin_spec
             # Construct name based on side, pin name, and bit # in vector
             name = f'we_{pin}[{i * width + bit}]'
             chip.set('constraint', 'pin', name, 'side', 1)
-            chip.set('constraint', 'pin', name, 'order', order_offset + pin_order)
+            chip.set('constraint', 'pin', name, 'order', ea_pins - (order_offset + pin_order))
 
     # Repeat the same logic for each of the other 3 sides, with positions/axes
     # adjusted accordingly...
-    for i in range(we_pads.count(GPIO)):
+    no_pins = len(pins) * no_pads.count(GPIO)
+    for i in range(no_pads.count(GPIO)):
         order_offset = len(pins) * i
         for pin_order, pin_spec in enumerate(pins):
             pin, bit, width = pin_spec
             # Construct name based on side, pin name, and bit # in vector
             name = f'no_{pin}[{i * width + bit}]'
             chip.set('constraint', 'pin', name, 'side', 2)
-            chip.set('constraint', 'pin', name, 'order', order_offset + pin_order)
+            chip.set('constraint', 'pin', name, 'order', no_pins - (order_offset + pin_order))
 
+    we_pins = len(pins) * we_pads.count(GPIO)
     for i in range(we_pads.count(GPIO)):
         order_offset = len(pins) * i
         for pin_order, pin_spec in enumerate(pins):
             pin, bit, width = pin_spec
             # Construct name based on side, pin name, and bit # in vector
             name = f'ea_{pin}[{i * width + bit}]'
             chip.set('constraint', 'pin', name, 'side', 3)
-            chip.set('constraint', 'pin', name, 'order', order_offset + pin_order)
+            chip.set('constraint', 'pin', name, 'order', we_pins - (order_offset + pin_order))
 
-    for i in range(we_pads.count(GPIO)):
+    so_pins = len(pins) * so_pads.count(GPIO)
+    for i in range(so_pads.count(GPIO)):
         order_offset = len(pins) * i
         for pin_order, pin_spec in enumerate(pins):
             pin, bit, width = pin_spec
             # Construct name based on side, pin name, and bit # in vector
             name = f'so_{pin}[{i * width + bit}]'
             chip.set('constraint', 'pin', name, 'side', 4)
-            chip.set('constraint', 'pin', name, 'order', order_offset + pin_order)
+            chip.set('constraint', 'pin', name, 'order', so_pins - (order_offset + pin_order))
 
 
 def __configure_padring_side(chip, side_pads, side_name):