Only synthesis

[suppamax]

I would like to do something like

1. synthesis
2. LEC

but I don't get how to do it.

First, I tried to setup a single step of synthesis via

    filename = 'top.v'
    toplevel = 'top'
    chip = siliconcompiler.Chip()
    chip.load_target('freepdk45_demo')
    chip.set('arg', 'step', 'syn')
    chip.set('design', toplevel)
    chip.set('mode', 'asic')
    chip.set('flow', 'yosys')
    chip.set('source', filename)

    chip.run()

But I get

Invalid flow: syn0 will not receive required input top.v.

I assumed the reason was a missing import step, so I tried with the first code snippet at this page, and adding a dummy flowname to the chip.node() functions, but then chip.run() modifies newly defined flows to single step ones and complains that no arg has been defined for a single tool flow. I think I even tried this approach with a pre-defined flowname (probably asicflow), the result didn't change.

[aolofsson]

Thanks for trying the tool! We may need to put a disclaimer on the arg, step parameter. It's really a scratch parameter for internal use and not really intended for the user. The following snippet should work.(verified).

The target sets up the whole flow and if you want to run a subset, you can specify a steplist to run. Important to note that you need to include all steps in the flow up to that point, including the required 'import' step that copies files into the compilation directory.

Aso, note that the LEC flow is experimental for now.

import siliconcompiler
filename = 'gcd.v'
toplevel = 'gcd'
chip = siliconcompiler.Chip()
chip.load_target('freepdk45_demo')
chip.set('design', toplevel)
chip.set('source', filename)
chip.set('steplist',['import','syn'])
chip.run()

[nmoroze]

Following up on this answer, to make a custom flow that does synthesis and LEC, I just tried this and confirmed it works. However, there's a small bug, you'll need the change in PR #921.

import siliconcompiler

chip = siliconcompiler.Chip()

chip.set('design', 'foo')
chip.load_target('freepdk45_demo')

flow = 'synlec'
chip.node(flow, 'import', 'surelog')
chip.node(flow, 'syn', 'yosys')
chip.node(flow, 'lecjoin', 'join')
chip.node(flow, 'lec', 'yosys')

chip.edge(flow, 'import', 'lecjoin')
chip.edge(flow, 'import', 'syn')
chip.edge(flow, 'syn', 'lecjoin')
chip.edge(flow, 'lecjoin', 'lec')

chip.set('flow', flow)

chip.write_flowgraph('flow.png')

chip.add('source', 'foo.v')

chip.run()

The API for setting up flows changed a bit, so unfortunately that docs page is out of date. Sorry about that, I will take care of it!

[suppamax]

Thanks, this is also very helpful