SC 'place' step and issue with small Verilog designs

[AllenDBoston]

Hi everyone,

I have been experimenting with generating small Verilog designs (2 bit adder, inverter) in SC. I have found that when the Verilog design is small SC has trouble in the 'place' step(OpenRoad). To further elaborate on my issue I have attached my build.py scrip and the corresponding Verilog for the inverter. (The inv.sdc is the same as heartbeat example.)

Python

# define the chip instance, target, and design name
chip = siliconcompiler.Chip(loglevel='INFO')

chip.load_target("skywater130_demo")


chip.set('source', 'inv.v')
chip.set('design', 'inv')

chip.add('constraint', "inv.sdc")

# Options
chip.set('relax', 'true')
chip.set('quiet', 'true')

#chip.set('eda', 'openroad', 'variable', 'place', '0', 'place_density', ['0.80'])

fp = floorplan.Floorplan(chip)
fp.create_diearea([(0, 0), (0, 0)], [(0, 0), (0, 0)], [(0, 0), (0, 0)])
chip.set('asic', 'diearea',  [(0,0), (3.5, 3.5)])
chip.set('asic', 'corearea', [(0.5,0.5), (3, 3)])

chip.run()
chip.summary()
fp.write_lef("inv.lef")
fp.write_def("inv.def")

chip.show()

Verilog

module inv (in, out);
input  [0:0] in;
output [0:0] out;

assign out = ~in;

endmodule

Issue:

With diearea = [(0, 0), (5, 5)], core area = [(1, 1), (4, 4)]
I get an error in the place step with the following message:

Note that smaller coreareas/dieareas will result in an error that says there is not enough core area for the design. Therefore if I increase the size I have a density issues as shown here:

Experimenting with the chip.set('eda', 'openroad', 'variable', 'place', '0', 'place_density', ['0.80']) function results in other errors related to floorplanning.

When I experiment with the coreareas/dieareas for the inverter design I find that using my script there is no working size for this design and this is common to other Verilog designs that are small (2 bit adder, AND gate). When I utilize other larger designs like a JTAG tap controller for example my script works perfectly. Any suggestions for sucessfully implementing smaller Verilog design using siliconcompiler. This may be more related to OpenRoad since this is the tool where the flow is hanging up. However, any suggestions would be appreciated.

Thank you

[nmoroze]

I believe I've heard about OpenROAD having problems with very small designs, and seen alterations to the flow that allow it to handle them more easily. However, I'm having trouble finding them at the moment.

One thing I'm curious about, if you get rid of the explicit chip.set('asic', 'diearea', ...) and chip.set('asic', 'corearea', ...) calls, does that work? Without those included, the built-in flow will infer an area based on synthesis results.

Finally, I noticed in your script that you set up a floorplan using the Floorplanning API but don't feed it into your chip object. To get the chip object to actually use a floorplan designed using the API, you need to call write_def() before the run() step and then feed it in by doing chip.set('read', 'def', 'floorplan', '0', 'inv.def'). See my answer in #893 for an example with this.

[AllenDBoston]

Thank you. I have since heard about OpenROADs problem with small designs. Getting rid of the explicit diearea and corearea calls has no effect on the type of error thrown when running sc with small designs. The answer in #893 is very useful so I will transition most of my further discussions to that thread.

[mithro]

Please report issues with OpenROAD like it not handling small designs upstream. OpenROAD should work with trivial and small designs.