hierarchical flow w/ place_macro()

[AllenDBoston]

Hi everyone,

I am looking for some guidance on correctly using the place macro function. Specifically more information on choosing the correct instance and module name. Are there any good examples other than the floorplaning tutorial to demonstrate the usage of place_macro() function? I have successfully placed macros from the zerosoc example with this function on a top level Floorplan. However, my goal is to execute a hierarchical flow first with the basic steps:

1. Generating .lef, .gds, and .vg for a design using siliconcompiler.
2. Use these files to place the design as a macro in a bigger Floorplan also in siliconcompiler.

Thanks.

[nmoroze]

Hi, good question! The full ZeroSoC build script does something like this, but there's a lot going on there. Here's a minimal example that should help demonstrate the key parts:

asic_core.v - the child design

module asic_core();

    // Insert implementation here

endmodule

asic_top.v - the larger design that integrates asic_core

module asic_top();

    asic_core myinstance ();

    // Additional implementation here

endmodule

asic_core.bb.v - a blackboxed asic_core.v (you'll see the reason for this shortly)

(* blackbox *)
module asic_core(
    // instantiate same IO as in asic_core.v
);
    // no implementation, this is a blackbox!
endmodule

build_core.py - build script for asic_core

import siliconcompiler
from siliconcompiler.floorplan import Floorplan

import shutil

chip = siliconcompiler.Chip()

chip.set('design', 'asic_core')

chip.load_target('skywater130_demo')

# Set up sources and anything else
chip.add('source', 'asic_core.v')
# ...

fp = Floorplan(chip)

# Set up floorplan here...

# Generate a DEF and LEF for design
fp.write_def('asic_core.def')
fp.write_lef('asic_core.lef')

# Feed generated DEF into floorplanning step
chip.set('read', 'def', 'floorplan', '0', 'asic_core.def')

# Run build
chip.run()

# Copy generated files out of build directory into current working directory
gds = chip.find_result('gds', step='export')
netlist = chip.find_result('vg', step='dfm')
shutil.copy(gds, 'asic_core.gds')
shutil.copy(netlist, 'asic_core.vg')

build_top.py - build script for asic_top

import siliconcompiler
from siliconcompiler.floorplan import Floorplan

chip = siliconcompiler.Chip()

chip.set('design', 'asic_top')

chip.load_target('skywater130_demo')

chip.add('source', 'asic_top.v')
# Here is where we need the black-box Verilog module for macro.
chip.add('source', 'asic_core.bb.v')
# ...anything else here

# Before floorplanning, we need to set up the child design as a library. 
# This is where we specify the paths to the LEF, GDS, and vg.
chip.add('asic', 'macrolib', 'asic_core')
stackup = chip.get('asic', 'stackup')
chip.set('library', 'asic_core', 'lef', stackup, 'asic_core.lef')
chip.set('library', 'asic_core', 'gds', stackup, 'asic_core.gds')
chip.set('library', 'asic_core', 'netlist', 'verilog', 'asic_core.vg')

fp = Floorplan(chip)

# Place asic_core in asic_top. Note: the instance name needs to match the name of the 
# asic_core instance in asic_top.v, and the module name matches the name of the 
# asic_core module itself.
fp.place_macros([('myinstance', 'asic_core')], ...)

# Additional floorplanning here...

fp.write_def('asic_top.def')

chip.set('read', 'def', 'floorplan', '0', 'asic_top.def')

chip.run()

Importantly, running build_core.py first will generate a DEF and LEF using the floorplan API, and then generate a GDS and VG from the DEF/sources by running the asicflow. It copies out the results from the build directory into the working directory.

build_top.py then sets up a library in its chip object that points at these generated files in the current working directory. In the place_macros() function, the instance name is the name of the child instance in asic_top.v, and the module name is just the name of the asic_core Verilog module itself.

I hope this is helpful, let me know if you have any questions about this or if anything comes up. Good luck!

[AllenDBoston]

So I have given this a try and since ran into another bug. Here^ build_core.py is working great however there is trouble with build_top.py. My problem begins with this line:

chip.set('library', 'asic_core', 'lef', stackup, )

where I get the error:

| ERROR | job0 | --- | - | Set/Add keypath [library,adder,lef,5M1LI] does not exist.

Any help would be appreciated.
Thank you

[nmoroze]

What version of SC are you using? If you pulled the source from the repo a commit hash would be useful, otherwise if you installed using pip, what is the result of running sc -version? Some of the schema keypaths have been changing slightly, so I could have given you snippets for the wrong version.

[AllenDBoston]

Version 0.6.0

[nmoroze]

Ah yeah, this keypath changed in version 0.7. Can you upgrade with pip install --upgrade siliconcompiler?