Mixed-signal

[ali-zeinolabedin]

Hi,

May I double-check with the SiliconCompiler team that the mixed-signal project can be done with it?
My example is a digital on-top design with 64 ADCs as an analog macro at 130nm. I'd like to have a digital top-level and add the analog macros and let the tool do the backend. I am wondering if SC can handle this kind of design process and create the sdf-generated netlist.

Could you let me know if there is any open-source tool to do the post-layout netlist simulation? Does icarus support that?

Regards,
Ali

[gadfort]

Hi @ali-zeinolabedin ,

At the moment we would support atleast the physical flow assuming the ADCs are hardIPs and you are not expecting to use SC to build those as well.
We can write out a SPEF file at the moment, but it would be fairly easy to add SDF generation as well from OpenROAD.
Icarus looks to have support for SDF (https://iverilog.fandom.com/wiki/Vvp_Flags#SDF_Support), We have support for icarus, but not the SDF annotation, so those flags would just need to be implemented to handle that correctly.

[gadfort]

@ali-zeinolabedin OpenROAD will now write the SDF files: #1832
The simulators still need to be able to use them, but it's a start