Is there a way to read in a DEF and use SiliconCompiler to route it?

[jarvis-lorry]

Is there a way to have SC read in a DEF generated from another tool and have SC route the design? The DEF would contain all of the placed cells, the clock tree elements, and routed metal lines that would be removed before rerouting.

[nmoroze]

Good question! To do this now, one would have to either:

1. hack up our existing asicflow a bit to start with "route" and provide a DEF directly to that step or
2. create a new flow that runs whatever tools are required to produce the DEF, then runs the OpenROAD route step

(1) is probably the easiest way to get started. I haven't had a chance to fully test this yet, but you'll want to do something like:

• in flows/asicflow.py:
  • delete/comment out every step up to "route" in longpipe: https://github.com/siliconcompiler/siliconcompiler/blob/main/siliconcompiler/flows/asicflow.py#L70-L83
  • replace this line: https://github.com/siliconcompiler/siliconcompiler/blob/main/siliconcompiler/flows/asicflow.py#L123 with ('import', 'nop') to skip the Verilog pre-processing import step
• Provide a DEF file in your build script like so: chip.set('input', 'def', 'path-to-def')

You may also have to do a bit of tweaking the OpenROAD TCL scripts in case there's some mismatch in expectations of DEF contents. This should be a good place to start however.

We can also think about ways to make this easier going forward - I think we want SC to be usable for doing these sorts of experiments in a clean way.

[jarvis-lorry]

Thank you, @nmoroze.
I have figured out a way to do this myself by running OpenROAD outside of SC. I've found that I had to hack the routed DEF file to remove all of the routed metal lines, leaving only the placed cells including clock tree buffers.

If I need to reroute, I will use approach #1, which you've laid out as I understand the pitfalls now.