load library

[ValeriiPlumerai]

Hi
I was trying to load lib in such a way, same as described in documets :

    lib = siliconcompiler.Chip('mylib')
    lib.add('model', 'layout', 'lef', 'dti_tm16ffc_90c_7p5t_stdcells_rev1p1p0.lef')

But unfortunately, I get such an error:

Traceback (most recent call last):
  File "/home/valerii/work/sc/siliconcompiler/heartbeat/heartbeat.py", line 52, in <module>
    main()
  File "/home/valerii/work/sc/siliconcompiler/heartbeat/heartbeat.py", line 5, in main
    lib.add('model', 'layout', 'lef', 'dti_tm16ffc_90c_7p5t_stdcells_rev1p1p0.lef')
  File "/home/valerii/work/sc/venv/lib/python3.10/site-packages/siliconcompiler/core.py", line 939, in add
    return self._search(cfg, keypathstr, *all_args, field=field, mode='add')
  File "/home/valerii/work/sc/venv/lib/python3.10/site-packages/siliconcompiler/core.py", line 1153, in _search
    return self._search(cfg[param], keypath, *all_args, field=field, mode=mode, clobber=clobber)
  File "/home/valerii/work/sc/venv/lib/python3.10/site-packages/siliconcompiler/core.py", line 1153, in _search
    return self._search(cfg[param], keypath, *all_args, field=field, mode=mode, clobber=clobber)
  File "/home/valerii/work/sc/venv/lib/python3.10/site-packages/siliconcompiler/core.py", line 992, in _search
    list_type =bool(re.match(r'\[', cfg[param]['type']))
KeyError: 'type'

Any suggestion?

[nmoroze]

Sorry about that, looks like a mistake in the docs! The ['model', 'layout', ...] keypath requires an additional "stackup" key after the filetype:
https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#model-layout.

So the correct line would look something like:
lib.add('model', 'layout', 'lef', stackup, 'dti_tm16ffc_90c_7p5t_stdcells_rev1p1p0.lef')
where stackup is the PDK stackup name that the LEF file is compatible with.

[ValeriiPlumerai]

sure
I'll post it here

import siliconcompiler                            # import python package

def main():
    lib = siliconcompiler.Chip('mylib')
    lib.set('asic','stackup','dti')
    lib.add('model','layout','lef', 'dti', 'dti_tm16ffc_90c_7p5t_stdcells_rev1p1p0.lef')
    lib.add('model','layout','gds', 'dti', 'dti_tm16ffc_90c_7p5t_stdcells_rev1p1p0.gds')


    chip = siliconcompiler.Chip('design')                 # create chip object
    chip.set('input', 'verilog', 'ikva_top.v')

    chip.add('input', 'verilog', 'efx_fifo_wrapper.v')
    chip.add('input', 'verilog', 'bin2gray.v')
    chip.add('input', 'verilog', 'efx_asyncfifo_ctl.v')
    chip.add('input', 'verilog', 'gray2bin.v')
    chip.add('input', 'verilog', 'simple_dual_port_ram_fifo.v')
    chip.add('input', 'verilog', 'dmif_enable.v')
    chip.add('input', 'verilog', 'efx_fifo_ctl_sm.v')
    chip.add('input', 'verilog', 'efx_syncfifo_ctl.v')
    chip.add('input', 'verilog', 'efx_fifo_functions.vh')
    chip.add('input', 'verilog', 'pipe_reg.v')
    chip.add('input', 'verilog', 'mem_family.v')
    chip.add('input', 'verilog', 'ram_ctrl.v')
    chip.add('input', 'verilog', 'mem_wrapper.v')
    chip.add('input', 'verilog', 'work_ram.v')
    chip.set('design', 'ikva_top')               # set top module
    chip.set('input', 'sdc', 'heartbeat.sdc')       # set constraints file

    chip.import_library(lib)
    chip.add('asic', 'macrolib', 'mylib')
    chip.run()                                    # run compilation
    chip.summary()                                # print results summary
    chip.show()                                   # show layout file

if __name__ == '__main__':
    main()

[nmoroze]

Got it, looks like the problem is you haven't loaded a flow (or PDK, for that matter).

Taking a step back, what is your goal with this script? In particular, what target are you trying to compile for? That context might help me more efficiently point you in the right direction.

For some general information, you can use one of our predefined targets to handle flow/PDK configuration if you're looking to build for one of the open PDKs we support. For example, chip.load_target('freepdk45_demo'), configures the chip object to do RTL2GDS for the FreepPDK45 PDK.

However, since your library names mention standard cell libraries, I wouldn't be surprised if you're trying to target a different one? In that case, you'll have to configure the PDK yourself. Here's a bit of info that might be helpful there: https://docs.siliconcompiler.com/en/latest/user_guide/pdks.html.

Also note that standard cell libraries should be added to the ['asic', 'logiclib'] parameter, rather than macrolibs:
chip.add('asic', 'logiclib', 'mylib')

[ValeriiPlumerai]

• I started with the example heartbeat design and used it as a base.
• Later I replaced sources with my files
• So the following step that I want to switch from FreePDK45 to external standard cell lib

[nmoroze]

Got it! So are the standard cells that you're trying to provide alternate cells for FreePDK45, or are they associated with a different PDK?

[ValeriiPlumerai]

they associated with a different PDK
Should I configure it?