rits-drsl
Dynamic Reconfigurable System Lab., Ritsumeikan Univ.
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ZybotR2-96-fpt19
ZybotR2-96-fpt19 PublicAn UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019
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ZybotR2-96-fpt19-bsp
ZybotR2-96-fpt19-bsp PublicBoard Support Packages for rits-drsl/ZybotR2-96-fpt19
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- ZybotR2-96-fpt19 Public
An UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019
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