drm: rp1: rp1-dsi: Switch to PLL_SYS source for DPI when 8*lanes > bpp #6136
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6by9
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Apr 30, 2024
The "bogus fixed clock" is also something I really ought to fix -- probably by making a near clone of |
To support 4 lanes, reparent DPI clock source between DSI byte-clock (which is declared to run at a dummy rate) and PLL_SYS (at real 200MHz). This requires DSI to know about PLL_SYS; updated this in rp1.dtsi. Tidying: All frequencies now in Hz (not kHz), where DSI speed is now represented by byte_clock to simplify arithmetic. Clamp DPI and byte clocks to their legal ranges; remove the lower bound on HSTX timeout. Change the "dummy" byte-clock frequency from 72MHz to 72kHz, to more easily distinguish it from real clock frequencies. The resulting DSI output appears largely correct, but line timings become slightly irregular at most pixel rates. For reasons not yet understood, RP1 DSI still doesn't work with LT070ME05000. Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
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Add a new class of clocks to RP1 to represent clock sources whose frequencies change at run-time as a side-effect of some other driver. Remove the "dummy" 72kHz clock sources from rp1.dtsi. Set the actual MIPI byte clock frequency from RP1 DSI driver. (These changes should be made atomically). Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
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I've left the clocking changes unsquashed, for clarity. There are changes in several places which kinda need to be atomic. |
clk-rp1 changes look reasonable to me. Shame there is not an existing clock type like this in the framework. |
Set HSTX timeout to the whole vertical active region, not just one line. For this, the divider must be increased, which affects the LPRX timeout (but not the BTA one). Disable the timeout altogether when too long. Disable returning to LP state during HBP, when sync pulses are required and we can't do accurate DPI timing. This should guarantee that the Hsync->Data interval is a fixed number of DSI clocks in those cases. Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
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Replaced by #6157 |
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Draft which partially addresses #6125.
This sets up the DPI clock as accurately as it can to match the DSI rate; without altering HS/LP transitions or messing with the mode timings.
If 4-lane panels are as fussy as the bridge chip in our (1-lane) 7" display, there is a risk of horizontal jitter, due to irregular line intervals at most pixel-clock rates.
Not yet successfully tested with any real 4-lane panel.