1. Introduction to On-chip clock multiplier

This repository contains simulation files and other relevant files on the On-chip clock multiplier using PLL (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v) IP worked on in the VSD Online Internship.

The target is to design a On-chip clock multiplier using the osu180nm technology node. The specifications are provided from VSD Corporation Pvt. Ltd. The On-chip clock multiplier is present in almost all synchronous processor chips (Integrated circuits).

Table of Contents

• 1. Introduction to On-chip clock multiplier
• 2. Theory
• 3. Specification List
• 4. EDA Tools Used
• 5. Pre-layout Simulations
• 6. Post-layout and Simulations
• 7. Future work
• 8. Author
• 9. Contributors
• 10. Acknowledgments
• 11. Contact Information -

2. Theory

The clock generator is one of the most crucial part in synchronous processor & probably most susceptible after power lines which can cause failure of entire circuitry if not designed properly.

The phase locked loop or PLL is a circuit block that is widely used in radio frequency or wireless applications.

In view of its usefulness, the phase locked loop or PLL is found in many wireless, radio, and general electronic items from mobile phones to broadcast radios, televisions to Wi-Fi routers, walkie talkie radios to professional communications systems etc.

the circuit simulated here uses PLL block to get desired frequency at it’s output (which is 8 times to that of input frequency provided). This IP block can be used for clock distribution for processor chip.

3. Specification List

Parameter	Description	Min	Type	Max	Unit	Condition
VDD	Digital supply voltage		1.8		V	T=-40 to 150C
FCLKREF	Reference clock frequency	5	10	12.5	MHz
FCLKOUT	Output clock frequency	39.7	80.91	99.81	MHz	PLL mode, T=27C, VDD=1.8
FCLKOUT	Output clock frequency				MHz	VCO mode, T=27C, VDD=1.8
DC	Duty Cycle	48		52	%	T=-40 to 150C
IBCP	Bias current for VCO				uA
VVCO	Oscillatror control input voltage	.557		0.62	V	Vin_vco = 0V at t = 0 (.uic)
JRMS	Jitter (rms)		future work		ps	PLL mode, FCLKREF = 10MHz
TSET	Settlng Time	5.2	5	4.6	us	start from EN_CP and report 2 values; one at FCLKOUT=40MHz and one at FCLKOUT=100MHz
CL	Load Capacitance				pF
IDDA	Analog Supply current				ua	VVCO=0.8V, VCO mode
IDDA	Analog Supply current				ua	FCLKREF=10MHz, PLL mode
IDDA	Analog Supply current				pa	EN_VCO=0, EN_CP=0, FCLKREF=0
IDDD	Digital Supply Current				uA	VVCO=0.8V, VCO mode
IDDD	Digital Supply Current				uA	FCLKREF=10MHz, PLL mode
IDDD	Digital Supply Current				uA	EN_VCO=0, EN_CP=0, FCLKREF=0

4. EDA Tools Used

The design has been built using open-source EDA tools. The library used is osu180nm.

1. Ngspice
2. Magic

5. Pre-layout Simulations

The complete circuit of PLL is built hierarchically using the following subcircuit blocks.

Fig: Block Diagrm of PLL Design.

Fig: Input-Output waveforms from Pre-layout Simulation.

Fin - Input Frequency. (Red)

up - Up signal (Blue)

down - Down signal (Yellow)

Vcp - Input Voltaage of VCO (Green)

fout - Output Frequency (Pink)

Pre-layout Simulation Results

Input Frequency	Output Frequency
5MHz	39.73MHz
10MHz	80.91MHz
12MHz	96.1MHz
12.5MHz	99.81MHz

6. Post-Layout Simulations

A. Phase Frequency Detector

Fig: Layout of Phase Frequency Detector (PFD) or Phase Detector (PD)

Fig: Input-Output waveforms of Phase Frequency Detector (PFD) or Phase Detector (PD)

Inputs - Fin (Input Frequency) & Fvco_8 (Output Frequency divide by 8)

Outputs - Up Signal & Down Signal

B. Voltage Controlled Oscillator

Fig: Layout of Voltage Controlled Oscillator (VCO).

Fig: Input-Output waveforms of Voltage Controlled Oscillator (VCO).

Vin - Input Voltage

Fout - Output Frequency

C. Frequency Divider by 2

Fig: Layout of Frequency Divider by 2.

Fig: Input-Output waveforms of Frequency Divider by 2.

clk - Input Freqency.

q - Output Freqency (Input Freq. by 2).

D. Frequency Divider by 8

Fig: Layout of Frequency Divider by 8.

Fig: Input-Output waveforms of Frequency Divider by 8.

clk - Input Freqency.

q - Output Freqency (Input Freq. by 8).

E. 2:1 MUX

Fig: Layout of 2:1 MUX.

Fig: Input-Output waveforms of of 2:1 MUX.

i1 - Input 1

i2 - Input 2

sel - Select

out - Output

F. Phase lock Loop

Fig: Layout of Phase Lock Loop (Combining all the Sub-circuits of PLL).

a. Input frequency = 5MHz

Fig: Input-Output waveforms of PLL.

Fin - Input Frequency. (Top Red)

Fvco_8 - Output Frequency divide by 8. (Blue)

up - Up signal (Yellow)

down - Down signal (Green)

Vcp - Input Voltaage of VCO (Pink)

fout - Output Frequency (Bottom Red)

Fig: Input-Output waveforms of PLL.

Fin - Input Frequency. (Red)

fout - Output Frequency (Blue)

b. Input frequency = 10MHz

Fig: Input-Output waveforms of PLL.

Fin - Input Frequency. (Top Red)

Fvco_8 - Output Frequency divide by 8. (Blue)

up - Up signal (Yellow)

down - Down signal (Green)

Vcp - Input Voltaage of VCO (Pink)

fout - Output Frequency (Bottom Red)

Fig: Input-Output waveforms of PLL.

Fin - Input Frequency. (Red)

fout - Output Frequency (Blue)

c. Input frequency = 12.5MHz

Fig: Input-Output waveforms of PLL.

Fin - Input Frequency. (Top Red)

Fvco_8 - Output Frequency divide by 8. (Blue)

up - Up signal (Yellow)

down - Down signal (Green)

Vcp - Input Voltaage of VCO (Pink)

fout - Output Frequency (Bottom Red)

Fig: Input-Output waveforms of PLL.

Fin - Input Frequency. (Red)

fout - Output Frequency (Blue)

Note: As there were limitaions for for layout of capacitor in OSU180 tech file, I'm unable to make layout of Low Pass Filter. However, using more mature & advanced nodes & PDK tech file, it can be made on silicon.

7. Future work

1. Porting this IP on lower technology nodes using advance PDK's where capacitor fabrication is realizable
2. Area Efficient Design Improvements.
3. Improvements for Power Reduction.
4. Improvements of accuracy, jitter & dead zone.

8. Author

• Paras Gidd, M.Tech.( Microelectronics ), Manipal Institute of Technology,(MAHE), parasgidd@gmail.com

9. Contributors

• Paras Gidd
• Kunal Ghosh
• Philipp Gühring

10. Acknowledgments

• Kunal Ghosh, Co-founder VSD Corp. Pvt. Ltd.

• Philipp Gühring, Software Architect, LibreSilicon Association.

• FOSSEE Team, IIT Bombay

• R. Timothy Edwards, Open Circuit Design

• Gerald Topalli - who helped me with basics of PLL & phase locking.

  I would also like to thank research fellows for extending their help and guidance during the research internship program. They have their own projects & if you are interested in those projects have a look in the links provided below.

• Sheryl Serrao - 10 bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

• Reuel Reuben - SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM)

• Ananya Ghorai - 10 bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

• Yash Kumar - SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM)

• Neethu Johny - 10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

• Ashutosh Sharma - 10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

And Last but not least, I would like to thank my Parents & Teachers who directly & indirectly helped me & their contribution is of great value for me.

11. Contact Information -

• Paras Gidd, M.Tech.( Microelectronics ), Manipal Institute of Technology,(MAHE), parasgidd@gmail.com
• Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd. - kunalghosh@gmail.com
• Philipp Gühring, Software Architect, LibreSilicon Association - pg@futureware.at