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Purpose of AXI_BUS, axi_master_connect dependency with axi_switch_vif in uvm_testbench #2071

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dvusingh opened this issue Apr 23, 2024 · 6 comments
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@dvusingh
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Hi,

I observed that in the cva6_tb_wrapper.sv file,

  1. we are connecting axi_interface signal based on axi_switch_vif as done in below assign statement
    **assign axi_ariane_resp.aw_ready = (axi_switch_vif.active) ? axi_slave.aw_ready : cva6_axi_bus.aw_ready;

Now again we are doing the same assignment, as axi_switch_vif.active =1
assign axi_slave.aw_ready = (axi_switch_vif.active) ? axi_slave.aw_ready : cva6_axi_bus.aw_ready;**

we have AXI_BUS instance and axi_master_connect instance

AXI_BUS.Master master
);
assign master.aw_id = dis_mem? '0 : axi_req_i.aw.id;
assign master.aw_addr = dis_mem? '0 : axi_req_i.aw.addr;

Here, master.aw_addr=0.

  1. later we are connecting the axi2mem with sram for instruction and data storage

What is the purpose of connecting AXI_BUS and axi_master_connect with cva6 using axi_switch_vif?

I am not able to understand this can anyone explain.

Thanks

@AEzzejjari
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Hello,

In our testbench, we have two slaves: the SRAM with AXI2MEM adapter connected to cva6_axi_bus, and the AXI slave agent connected to axi_slave. During simulation, we utilize only one slave.

The axi_switch_vif is created to toggle between the two slaves:

  • When the agent is in passive mode, we connect the SRAM to cva6, meaning cva6 receives input from cva6_axi_bus. In this scenario, the agent solely monitors all signals (thus, "assign axi_slave.aw_ready = (axi_switch_vif.active) ? axi_slave.aw_ready : cva6_axi_bus.aw_ready;").

  • When the agent is in active mode, it is responsible for setting the inputs of cva6 (hence, to switch between the two interfaces **assign axi_ariane_resp.aw_ready = (axi_switch_vif.active) ? axi_slave.aw_ready : cva6_axi_bus.aw_ready;).

@dvusingh
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dvusingh commented May 3, 2024

Hi,

I ran few testcases, but I found that the axi_slave is always in active mode.
Also, I found 1 more issue that relates: Passive mode of AXI agents does not work anymore #1946

Any clarification on this.

Thanks

@AEzzejjari
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Hi,

Like you said, there is a bug in the passive agent. Once it's fixed, you can use the agent in passive mode.

@dvusingh
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Hi,

Any updates on the passive mode agent's issue.

Thanks

@dvusingh
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dvusingh commented Jun 5, 2024

Hi,

I want to run my simulation with passive agents with SRAM support.
I want to collaborate to resolve the bug in passive agent in uvm-testbench. Any inputs how I should start to check the issue.

Thanks

@AEzzejjari
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Hi,

The problem is fixed now. You can try using the passive mode
Thank you

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