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Purpose of AXI_BUS, axi_master_connect dependency with axi_switch_vif in uvm_testbench #2071
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Hello, In our testbench, we have two slaves: the SRAM with AXI2MEM adapter connected to cva6_axi_bus, and the AXI slave agent connected to axi_slave. During simulation, we utilize only one slave. The axi_switch_vif is created to toggle between the two slaves:
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Hi, I ran few testcases, but I found that the axi_slave is always in active mode. Any clarification on this. Thanks |
Hi, Like you said, there is a bug in the passive agent. Once it's fixed, you can use the agent in passive mode. |
Hi, Any updates on the passive mode agent's issue. Thanks |
Hi, I want to run my simulation with passive agents with SRAM support. Thanks |
Hi, The problem is fixed now. You can try using the passive mode |
Hi,
I observed that in the cva6_tb_wrapper.sv file,
**assign axi_ariane_resp.aw_ready = (axi_switch_vif.active) ? axi_slave.aw_ready : cva6_axi_bus.aw_ready;
Now again we are doing the same assignment, as axi_switch_vif.active =1
assign axi_slave.aw_ready = (axi_switch_vif.active) ? axi_slave.aw_ready : cva6_axi_bus.aw_ready;**
we have AXI_BUS instance and axi_master_connect instance
AXI_BUS.Master master
);
assign master.aw_id = dis_mem? '0 : axi_req_i.aw.id;
assign master.aw_addr = dis_mem? '0 : axi_req_i.aw.addr;
Here, master.aw_addr=0.
What is the purpose of connecting AXI_BUS and axi_master_connect with cva6 using axi_switch_vif?
I am not able to understand this can anyone explain.
Thanks
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